Integrated Testing Methods and Techniques
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Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
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The deterioration of railway tracks raises great concerns about the integrity of assessments and evaluations of railway tracks currently in service. Integrated inspection strategies coupled with innovations in inspection technology can lead to significant improvements in operational cost efficiency and reliability without the requirement of a fundamental shift in the existing understanding o...
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The quality of the road pavement has always been one of the major concerns for governments around the world. Cracks in the asphalt are one of the most common road tensions that generally threaten the safety of roads and highways. In recent years, automated inspection methods such as image and video processing have been considered due to the high cost and error of manual metho...
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This article uses seasonal integration and co integration techniques to test the hypothesis of neutrality of money, using data from the Iranian economy. Seasonal data for the three variables of money supply, output and prices show that (increase in) money supply and the price level are co integrated at zero frequency, but one does not see such a relationship between (increase in) money supply a...
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System-on-chip is an integrated circuit comprising of numerous functional cores which can be of various types. Testing of such diverse circuit is very complex problem. Test access to digital cores is ensured by core wrapper architectures. The paper presents two novel contributions to core test wrappers: (1) the set of optimization techniques for parallel interface to provide faster test applica...
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